1. Field of the Invention
The present invention relates to a discrete cosine transform circuit which can be used in compression/extension processing of digital voice data in a digital voice recording and reproduction devices, and in particular to simplification of the circuitry structure.
2. Description of the Related Art
FIG. 1 is a block diagram showing a processing device which performs encoding/decoding of digitized voice data. At the time of recording, the entered voice signal is first converted to digital voice data by A/D (analog to digital) converter 2. The digital voice data is divided to three, low, medium, and high, frequency bandwidths using QMF (quadrature mirror filter) circuit 4. The digital time series voice data is converted to frequency component data using DCT (discrete cosine transform) circuit 6, and further quantized by a quantizing unit 8. The generated or encoded data is supplied to the next-stage processing circuit, and recorded in a predetermined recording medium.
At the time of reproduction, processing reverse to the processing described above is performed. Specifically, an inverse quantizing unit 10, IDCT (inverse discrete cosine transform) circuit 12, IQMF (inverse quadrature mirror filter) circuit 14 and D/A (digital to analog) converter 16 perform the conversion reverse to the conversion performed by the quantizing unit 8, DCT circuit 6, QMF circuit 4 and A/D converter 2. Specifically, a voice signal is reproduced from the recorded encoded data.
Additionally, DCT is useful for encoding/decoding voice signals, and it is widely used. There are various types of DCT. For example, there is one type of DCT for use in a voice recording/reproducing device which is represented by the following relational equation of 2M items of time series voice data y(n) represented by a time index n which is a continuous integer and M items of frequency component data X(k) represented by a wave number index k which is a continuous integer:                               y          ⁡                      (            n            )                          =                              ∑                          k              =              0                                      M              -              1                                ⁢                      xe2x80x83                    ⁢                                    X              ⁡                              (                k                )                                      ⁢                          cos              ⁡                              (                                                                            π                      ⁡                                              (                                                                              2                            ⁢                            k                                                    +                          1                                                )                                                              ⁢                                          (                                                                        2                          ⁢                          n                                                +                        M                        +                        1                                            )                                                                            4                    ⁢                    M                                                  )                                      ⁢                          xe2x80x83                        ⁢                          (                              0                ≦                n                 less than                                   2                  ⁢                  M                                            )                                                          (        1        )            
The DCT is slightly modified from a basic DCT and is therefor termed a Modified DCT, and will hereinafter be abbreviated as MDCT. Moreover, the inverse modified DCT is hereinafter abbreviated as IMDCT.
As an algorithm for processing DCT at a high rate, a method is known in which FFT (fast Fourier transform) is used. By the algorithm using FFT, sequence y(n) is obtained from sequence X(k) in the MDCT. Conversely, sequence X(k) is obtained from sequence y(n) in IMDCT.
More specifically, the relational equation (1) of the time series voice data y(n) and the frequency component data X(k) is represented in a format suitable for the calculation of IMDCT. For MDCT, calculation is performed based on equation (6) below.
The calculation algorithm regarding IMDCT based on the equation (1) will be described hereinafter. First, the data before conversion, i.e., sequence X(k) is re-arranged and re-constructed according to the predetermined rule to define a new sequence U(k). Based on U(k), Z(j) represented in the following equation is defined. Additionally, in the equation, i denotes an imaginary number unit, and "psgr"(j) denotes the predetermined function of j.
Z(j)=(U(2j)+iU(2j+1)xc2x7exp(i"psgr"(j))xe2x80x83xe2x80x83(2)
Furthermore, z(n) defined by the following equation is obtained from Z(j).                               z          ⁡                      (            n            )                          =                              ∑            j                    ⁢                                    Z              ⁡                              (                j                )                                      ⁢                          exp              ⁡                              (                                                      ⅈψ                    xe2x80x2                                    ⁡                                      (                    j                    )                                                  )                                                                        (        3        )            
In order to calculate the equation (3) at high speed, FFT is used. As is well known, FFT calculates the above equation (3) by repeating the arithmetic operation represented by the following equation. Additionally, "psgr"xe2x80x2(j) is the predetermined function of j.
Z(j1)+Z(j2)xc2x7exp(i"psgr"xe2x80x2(j) )xe2x80x83xe2x80x83(4)
In IMDCT, u(n) defined in the following equation (5) is obtained from the z(n), and the sequence u(n) is re-arranged and re-constructed to obtain the time series voice data y(n). Additionally, a0 to a3 are proportional coefficients defined for every n.
u(n)=a0xc2x7Rez
(n)+a1xc2x7Rez(M/2xe2x88x921xe2x88x92
n)+a2xc2x7Imz(n)+a3
xc2x7Imz(M/2xe2x88x921xe2x88x92
n))u(Mxe2x88x921xe2x88x92n)=
a2xc2x7Rez(n)xe2x88x92a3xc2x7Rez
(M/2xe2x88x92n)xe2x88x92a0xc2x7Imz(n)+
a1xc2x7Imz(M/2xe2x88x921xe2x88x92n)xe2x80x83xe2x80x83(5)
On the other hand, for MDCT, the following relational equation is used to obtain the frequency component data X(K) from the sequence x(n) based on the time series voice data y(n).                               X          ⁡                      (            k            )                          =                              2            M                    ⁢                                    ∑                              k                =                0                                            M                -                1                                      ⁢                          xe2x80x83                        ⁢                                                            x                  1                                ⁡                                  (                  n                  )                                            ⁢                              cos                ⁡                                  (                                                                                    π                        ⁡                                                  (                                                                                    2                              ⁢                              k                                                        +                            1                                                    )                                                                    ⁢                                              (                                                                              2                            ⁢                            n                                                    +                          M                          +                          1                                                )                                                                                    4                      ⁢                      M                                                        )                                                                                        (        6        )            
The equations (1) and (6) have substantially the same format except the coefficient 2/M. Therefore, the calculation algorithm of MDCT is expected to be similar to that of the IMDCT described above. In practice, the calculation algorithm of MDCT based on the equation (6) is as follows, and has points common with the IMDCT algorithm.
First, a new sequence xxe2x80x2(n) is defined by the sum (or difference) of the predetermined elements of the data before conversion, i.e., the sequence x(n) as shown in the following equation:
xxe2x80x2(n)=x(n1)+x(n2) or x(n1)xe2x88x92x(n2)xe2x80x83xe2x80x83(7)
Based on the xxe2x80x2(n), z(j) is defined in the following equation having the same format as that of the equation (2):
z(j)=(xxe2x80x2(2j)+ixxe2x80x2(2j+1))xc2x7exp(i"psgr"(j))xe2x80x83xe2x80x83(8)
Furthermore, Z(k) is obtained from the z(j) as defined in the following equation:
The equation (9) has the same format as that of the equation                               Z          ⁡                      (            k            )                          =                              ∑            j                    ⁢                                    z              ⁡                              (                j                )                                      ⁢                          exp              ⁡                              (                                                      ⅈψ                    xe2x80x2                                    ⁡                                      (                    j                    )                                                  )                                                                        (        9        )            
(3), FFT is also used in the high speed calculation in the same manner as in the equation (3),
and the arithmetic operation is performed in the following format:
z(j1)+z(j2)xc2x7exp(i"psgr"xe2x80x2(j))xe2x80x83xe2x80x83(10)
In MDCT, the frequency component data X(k) is obtained from the Z(k) by the following equation (11):
X(k)=b0xc2x7ReZ(k)+b1xc2x7ReZ
(M/2xe2x88x921xe2x88x92k) 
+b2xc2x7ImZ(k)+b3
xc2x7ImZ(M/2xe2x88x921xe2x88x92k) 
X(Mxe2x88x921k)=b2xc2x7ReZ
(k)xe2x88x92b3xc2x7ReZ(M/2xe2x88x921xe2x88x92
k)xe2x88x92b0xc2x7ImZ(k)+b1
xc2x7ImZ(M/2xe2x88x921xe2x88x92k)xe2x80x83xe2x80x83(11)
In the equation, b0 to b3 are proportional coefficients determined for each k. When the proportional coefficient aL(L=0 to 3) determined for each n is represented as aL=aL(n) or the proportional coefficient bL(L=0 to 3) is represented as bL=bL(k), the following relationship is established between the coefficients:
bL(j)=aL(j)xc3x972/Mxe2x80x83xe2x80x83(12)
FIG. 2 is a block diagram showing a conventional IMDCT circuit 1 in which the aforementioned IMDCT arithmetic operation is realized. The data before conversion, i.e., the frequency component data X(k), is stored in RAM (random access memory) 20. The RAM 20 is also constituted to store the results during the course of the arithmetic operation. For example, the proportional coefficient aL(L=0 to 3) is stored in ROM (read only memory) 22. The value read from RAM 20 and held in a register 26 and the value read from ROM 22 and held in a register 28 are transmitted to a multiplier 24, which multiplies these values to transmit them to either register 30 or 32.
An adder/subtracter 34 has two input terminals A, B, and is able to perform addition, i.e., xe2x80x9cA+Bxe2x80x9d, and subtraction, i.e., xe2x80x9cAxe2x88x92Bxe2x80x9d or xe2x80x9cBxe2x88x92Axe2x80x9d.
The inputs A and B are respectively connected to the selectors 36 and 38. The registers 26 and 30 are connected to the input side of the selector 36. Therefore, the selector 36 can selectively supply the data stored in RAM 20 or the data multiplied by the multiplier 24 to one input terminal A of the adder/subtracter 34. On the other hand, registers 42, 44 are connected to the selector 38 via a selector 40, while the register 32 is connected to the input side of the selector 38. Therefore, the selector 38 can selectively supply the value stored in the register 32 (e.g., the value obtained by multiplying the data stored in RAM 20 by the multiplier 24 ) or the output result of the adder/subtracter 34 to the other input terminal B of the adder/subtracter 34. The output of the adder/subtracter 34 can be returned and written to RAM 20 via the register 42.
In the conversion of the time series voice data y(n) and the frequency component data X(k), for the time series voice data y(n), consecutive 2M items of data are regarded as one block, and the data is handled block by block. One generated block of time series voice data is stored in RAM 44. In order to minimize the distortion of voice at boundaries of the blocks, the range of the block is determined in such a manner that the end of the preceding block and the top of the following block are overlapped with each other. In the overlapped area, the data values of these blocks are added to generate the final voice data y(n). To overlap the data, the voice data stored in RAM 44 can be returned to the adder/subtracter 34. Specifically, the value read from RAM 44 is transmitted to a selector 46 placed between the multiplier 24 and the register 32. The selector 46 selects the output of the multiplier 24 or the output of RAM 44 to transmit the selected value to the adder/subtracter 34 via the selector 38.
The aforementioned arithmetic operation in the conventional circuit will next be described. First, by developing the right side of the equation (2), Z(j) is represented in the following equation:
Z(j)=(U(2j)xc2x7cos "psgr"(j)xe2x88x92U(2j+1)xc2x7sin "psgr"(j))+i(U(2j+1)xc2x7cos "psgr"(j)xe2x88x92U(2j)xc2x7sin "psgr"(j))xe2x80x83xe2x80x83(13)
Therefore, when the data U(k) is stored in RAM 20, and sin "psgr"(j), cos "psgr"(j) are stored in ROM 22, the real-number and imaginary-number portions of Z(j) are calculated by successively using the multiplier 24 and the adder/subtracter 34. The operation results of the real-number and imaginary-number portions outputted from the adder/subtracter 34 are stored in RAM 20.
As described above, z(n) is obtained by repeating the arithmetic operation shown in the equation (4). When Z(j) stored in RAM 20 is transmitted to the adder/subtracter 34 via the register 26 and the selector 36 without passing through the multiplier 24, the first term on the right side of the equation (4) is supplied to one terminal A of the adder/subtracter 34. Moreover, the second term on the right side is generated by reading Z(j) stored in RAM 20 and exp(i"psgr"xe2x80x2(j)) stored in ROM 22 and multiplying them in the multiplier 24. The multiplied value is supplied to the other terminal B of the adder/subtracter 34 via the selector 46, the register 32 and the selector 38. The adder/subtracter 34 adds the first and second terms of the equation (4), and the result is stored in RAM 20. The calculation of z(n) is also a complex arithmetic operation, and the real-number portion and the imaginary-number portion are separately calculated in the circuit.
By the arithmetic operation described above, Rez(n), Rez(M/2xe2x88x921xe2x88x92n), Imz(n), Imz(M/2xe2x88x921xe2x88x92n) for use in the arithmetic operation of the equation (5) are stored in RAM 20. Moreover, the proportional coefficient aL (L=0 to 3) is stored in ROM 22. The calculation of the equation (5) is performed by sequentially calculating the terms from the first term on the right side by the multiplier 24 and cumulatively adding/subtracting the values by the adder/subtracter 34.
The calculation will be described in more detail. For example, Rez(n) is read from RAM 20 and stored in the register 26. On the other hand, a0 is read from ROM 22 and stored in the register 28. These values are multiplied in the multiplier 24 and stored in the register 32. Subsequently, Rez(M/2xe2x88x921xe2x88x92n) is read from RAM 20 and stored in the register 26, while a1, is read from ROM 22 and stored in the register 28. It is herein noted that the content of the register 26 is overwritten and changed from Rez(n) stored for the calculation of the first term to Rez(M/2xe2x88x921xe2x88x92n) for use in the calculation of the second term. The Rez(M/2xe2x88x921xe2x88x92n) and a1, are multiplied in the multiplier 24 and stored in the register 30. The adder/subtracter 34 calculates .A+B. in accordance with the contents of the registers 32 and 30 and transmits the result to the register 44.
Subsequently, the third term is calculated in the same manner as the first and second terms, and stored in the register 30. The adder/subtracter 34 calculates xe2x80x9cA+Bxe2x80x9d in accordance with the content of the register 30 and the cumulative added value up to the second term supplied from the register 44, and transmits an output to the register 44. The fourth term is calculated in the same manner, and added to the added value up to the third term, then the result is returned to RAM 20. Thereafter, the second equation of the equation (5) is calculated in the same manner as the first equation. In the calculation of the second equation, the second term transmitted to the input terminal A corresponds to the subtraction from the first term supplied to the input terminal B, and the adder/subtracter 34 performs xe2x80x9cBxe2x88x92Axe2x80x9d.
The structure and operation of the conventional IMDCT circuit have been described above. As described above, since the IMDCT arithmetic operation and the MDCT arithmetic operation have common parts, the conventional MDCT circuit structure is substantially the same as that of the IMDCT circuit shown in FIG. 2, and its operation is substantially the same as the aforementioned operation.
That is, a conventional IMDCT circuit such as described above comprises three selectors as main components for multiplication, addition, and subtraction. A typical MDCT circuit also has the same structure. Therefore, there is a problem that the structure of a conventional discrete cosine transformation circuit is complicated, and so is the structure of a timing generation circuit for controlling the circuit. This hinders reduction of the circuitry size. There is another problem that, when the adder/subtracter is constructed to have functions for achieving three types of calculations, namely, xe2x80x9cA+Bxe2x80x9d, xe2x80x9cAxe2x88x92Bxe2x80x9d, and xe2x80x9cBxe2x88x92Axe2x80x9d, the adder/subtracter has a large size.
The present invention has been conceived to overcome the above problems and aims to provide a discrete cosine transformation circuit including a timing generating circuit but having a simple circuitry structure. This is achieved by simplifying the structure of the main components for multiplication, addition, and subtraction, of the discrete cosine transformation circuit for executing discrete cosine transformation and inverted transformation.
According to the present invention, there is provided a discrete cosine transfer circuit (claim 1 second half) comprising
an addition-subtraction result register for holding an output from the adder/subtracter; and
an addition-subtraction result selector for outputting either content of the addition-subtraction result register or a value xe2x80x9c0xe2x80x9d,
an output of the multiplier being connected to the first input of the adder/subtracter,
an output of the addition-subtraction result selector being connected to the second input of the adder/subtracter,
the addition-subtraction result selector outputting the value xe2x80x9c0xe2x80x9d so that the addition-subtraction result register is loaded with the output of the multiplier in order to supply the output of the multiplier to the second input of the adder/subtracter.
In general, on the output side of an adder/subtracter, a number of registers for holding the arithmetic result are provided along with an addition/subtraction result selector for selecting reading from the registers. According to the present invention, the addition/subtraction result selector is constructed so as to output a value xe2x80x9c0xe2x80x9d as well as the content of the register connected thereto. An output from the addition/subtraction result selector is connected to the second input of the adder/subtracter, whose first input is connected to an output from the multiplier or the like. When a multiplication result is inputted from the multiplier into the first input of the adder/subtracter and xe2x80x9c0xe2x80x9d is inputted from the addition/subtraction result selector into the second input, it is possible to pass the multiplication result toward the output side of the adder/subtracter without changing the value thereof. Since the value can be further supplied to the second input of the adder/subtracter, it is not necessary to connect another output of the multiplication to the second input. When connection between the multiplier and the second input of the adder/subtracter is abolished, a selector which is conventionally provided on the second input side of the adder/subtracter for selecting either an output from the multiplier or an output from the addition/subtraction result selector becomes unnecessary.
Further, the above discrete cosine transformation circuit, (claim 2) further comprises
a calculation order controlling section for making adjustment such that multiplication of subtraction terms included in the addition/subtraction using terms based on the operand data by the multiplier and addition of multiplication results of the subtraction terms by the adder/subtracter are carried out before calculation using addition terms so that a total value of the subtraction terms is supplied to the adder/subtracter via the second input wherein
the adder/subtracter has only addition/subtraction functions of adding inputs via the first input and the second input, and of subtracting an input via the second input from an input via the first a input.
According to the present invention, when calculating, for example, xe2x80x9cAxe2x88x92B+Cxe2x88x92Dxe2x88x92Exe2x80x9d, the adder/subtracter first adds subtraction terms, namely xe2x80x9cBxe2x80x9d, xe2x80x9cDxe2x80x9d, and xe2x80x9cExe2x80x9d, and supplies the result xe2x80x9cB+D+Exe2x80x9d to the adder/subtracter via the second input terminal thereof. Subsequently, any one of the addition terms, e.g., xe2x80x9cAxe2x80x9d, is supplied to the adder/subtracter via the first input terminal so that the input via the second terminal is subtracted from that via the first terminal to thereby obtain xe2x80x9cAxe2x88x92Bxe2x88x92Cxe2x88x92Dxe2x80x9d. Then, remaining addition terms are added up. With this arrangement, it is sufficient for the adder/subtracter to have the functions only of adding inputs via the first and second input terminals and of subtracting an input via the second input terminal from that via the first terminal. In other words, the function of subtracting an input via the first input terminal from that the second input terminal can be eliminated.
According to the present invention, the above discrete cosine transformation circuit, (claim 3) further comprises
a proportional coefficient selector for supplying either the proportional coefficient or a value xe2x80x9c1xe2x80x9d to the first input of the multiplier, wherein
the proportional coefficient selector outputs the value xe2x80x9c1xe2x80x9d when a value of the operand data supplied to the adder/subtracter via the second input is used intact in the addition/subtraction.
According to the present invention, the multiplier receives a proportional coefficient via the first input terminal and an operand data via the second input terminal. On the first input terminal side of the multiplier, a proportional coefficient selector is connected. The proportional coefficient selector can desirably output a value xe2x80x9c1xe2x80x9d, besides proportional coefficients. Here, in discrete cosine transformation, there may be a case in which operand data is multiplied by a proportional coefficient before being supplied to the adder/subtracter and a case in which operand data is supplied intact to the adder/subtracter. According to the present invention, operand data is supplied to the multiplier in either case, and only in the latter case does, the proportional coefficient selector output the value xe2x80x9c1xe2x80x9d to be multiplied to the operand data so that the operand data is outputted intact to the subsequent adder/subtracter. With this arrangement, the input system to the first input of the adder/subtracter is unified. That is, a selector which is provided in a conventional circuit having different routs for supplying operand data intact to the adder/subtracter and for supplying from the multiplier, for switching the routes can be eliminated.